1. Field of the Invention
The invention relates to an electrically reprogrammable non-volatile memory device comprising an integrated circuit including complementary MOS transistors provided with a polycrystalline silicon floating gate electrode in a common n.sup.- -type grounded substrate.
2. Prior Art
Floating gate structures in which use of a floating gate (such as polycrystalline silicon floating gate electrode) is combined with avalanche electron injection are already known. Such structures have an extremely long memory retention time (several decades) owing to the fact that they are provided with relatively thick oxide layers. One memory device of this kind, which is commercially known under the name of FAMOS (floating-gate avalanche-injection MOS), has been developed by D. Frohman-Bentchkowsky and is described in Applied Physics Letters, pp. 332-334, volume 18, No. 8, published on Apr. 15, 1971. This kind of memory has the drawback that erasure can be performed only by subjecting the device to ultraviolet radiation or to X-rays.
Another device, which has been developed by Tarui et al. and which is described in IEEE Journal of Solid State Circuits, Volume SC-7, No. 5, October 1972, known under the name of two-junction type floating gate, consists of a p-channel transistor in which a n.sup.+ -p junction has been added in the channel portion. A second gate, made of aluminum, is provided over the floating gate. Writing is effected by injection of electrons by avalanche breakdown of the drain p.sup.+ -n junction, the second gate being either grounded or connected to a positive potential. Erasure is carried out by avalanche injection of holes which causes neutralization of the electron charge, the substrate being positive biased, the source being grounded and the second gate negative biased. One of the drawbacks of this kind of structure lies in the fact that injection of holes is a low efficiency and slow process. Furthermore, this type of structure is complicated and the substrate must be able to be positively biased.
One improvement of the FAMOS structure has been suggested by H. Iizuka et al. and described in IEEE Transactions on Electron Devices, volume ED-23, No. 4, published April 1976, under the name of SAMOS structure (Stacked-gate avalanche-injection type MOS). This structure is actually a FAMOS structure to which a second gate has been added in order to render it electrically erasable. Erasing is performed by Fowler-Nordheim effect between the first and second polycrystalline silicon gate by applying a high positive potential to the second gate which is called the control gate. In practice, it is difficult, in that kind of structure, to control the height of the potential barrier between the first and the second gate and one observes, during application of the charge and depending on the values of the voltages applied on the drain and on the second gate, that competition takes place between Fowler-Nordheim effect across the second gate and avalanche across the first gate.
Another structure, which has been developed by Jan F. Verwey et al. and is described in IEEE Transactions on Electron Devices, volume ED-21, No. 10, published October 1974 and known as ATMOS structure (Adjustable threshold MOS) comprises a n-channel transistor provided with a floating gate realized on an epitaxial p layer grown on a n.sup.+ -type substrate. This structure which has an excellent retention time and uses moderate voltage for the writing and erasing operations has the following drawbacks: necessity of using an epitaxial layer, relatively slow writing and erasing processes.
A structure called SIMOS, which has been developed by B. Roessler and R. G. Mueller, is described in the publication "Erasable and Electrically Reprogrammable Read-Only Memory using the N-Channel SIMOS One Transistor Cell" in Siemens Forschungs-und Entwicklungsberichten, Volume 4, No. 6, pp. 345-362, published in 1975 and, more recently in IEEE Transactions on Electron Devices, volume ED-24, No. 5 (May 1977) under the titles "Technology of a New n-Channel One-Transistor EAROM Cell Called SIMOS", by A. Scheibe and H. Schulte (p. 600), and "Electrically Erasable and Reprogrammable Read-Only Memory Using the n-Channel SIMOS One-Transistor Cell" by B. Roessler (p. 606). This memory is of the n-channel type with a double self-aligned polycrystalline silicon gate and it has the disadvantage of necessitating channel length of 3 to 4 .mu.m which is rather difficult to control. Writing operation is achieved by injection of electrons from the channel portion without pinchoff whereas erasure is performed by Fowler-Nordheim effect, a positive voltage ramp being applied on the MOST source which is partially overlaid with a thinner oxide layer of 500 A which is itself covered by the floating gate. Erasure time is of the order of one minute.
Finally, another structure, called DIFMOS, which has been developed by Texas Instruments Co., is described in an article bearing the title "La REPROM ultra-simple existe" (ultra-simple REPROM does exist), which was published in the revue Inter Electronique, volume 20, pages 16 to 22, in 1976 and more recently in IEEE Transactions on Electron Devices, volume ED-24, No. 5 (May 1977), page 594 by M. Gosney. This memory structure uses an aluminum floating gate. The write operation is performed by injection of electrons by avalanche of a p.sup.+ -n diode and the erase operation is carried out by hole-injection using a n.sup.+ -p junction while simultanously applying a negative voltage on a capacitor which drives the floating gate. The drawbacks of such a structure are the relatively high values of the writing and erasing currents (.about.0.5 m A), slow programming times and the fact that simultaneous application of two voltages is required for erasure. The cell has relatively large dimensions.
Generally, read-out of the above-described structures cannot be performed using such low voltages of the order of one volt. Adressing also requires higher voltages and realization of the corresponding structures often requires a special technology.